This invention relates generally to a method and apparatus for converting system signals and addresses from one configuration to a different configuration for use on DRAM memories. In more particular aspects, this invention relates to converting a single master or system RAS signal and the high order bit of a row address generated by a computer system from one configuration of memory addressing to two RAS signals useful in the system for a different memory addressing scheme.
High density memory systems are utilized to maximize performance in many PC server and work station environments. However, certain technological advances are costly to implement, and for certain implementations it is desirable to use less costly technology interchangeably with certain system configurations which can use higher technology. For example, sometimes it is desirable to use 16-meg chips with systems that support 64-meg technology. In such a configuration, a 64 or 72 bit wide data bus using 64-megabit (8M.times.8) chips can be used. If the system is designed for 8M.times.8 chips, the JEDEC standard is for a 12.times.11 address scheme (i.e., 12 row address bits and 11 column address bits). In such a scheme, only one bank is required to read all 64 or 72 bits, and thus only a single RAS signal is needed.
However, 64 megabit chips all utilize 3.3 volt technology which for several reasons is quite expensive and thus, while fewer chips can be used to store the same information, these fewer chips in the aggregate are more expensive than using 16 megabit chips manufactured in 5-volt technology. For example, eight 8M.times.8 chips can be used to store the same amount of information as is stored in 32 4M.times.4 chips. However, the 32 4M.times.4 chips are much cheaper in the aggregate than the eight 8M.times.8 chips, and thus for many applications, even though more chips are involved, it is desirable to use the 5-volt technology and 4M.times.4 chips.
Unfortunately, to achieve the same addressable space, 2 banks of 4M.times.4 DRAM chips are required which have an address configuration of 11 bit row addresses by 11 bit column addresses (11/11) but require 2 RAS signals to actuate the entire range. Expressed another way, 2 banks of 16 11.times.11 addressable 4M.times.4 DRAMs (for a total of 32 DRAMs) are necessary to provide the equivalent 8M address steps of 1 bank of 12/11 addressable 8M.times.8 DRAMs.
Moreover, the standard refresh technique for the 8M.times.8 technology using 3.3 volts is a CAS Before RAS (CBR) cycle. The current invention relates to CBR implementations.
SUMMARY OF THE INVENTION
According to the present invention, a method and logic circuit are provided which convert the high order address bit output from a computer system together with a single system RAS signal to two SIMM or DIMM RAS's such that a system configured to operate 1 bank of Y/X row/column addressable DRAMs with a single system RAS can operate 2 banks of Y-1/Z row addressable DRAM requiring 2 RAS signals and also provide CBR refresh.